Diode Packaging Mechanical Engineer
Location: Goleta, CA preferred. Remote candidates considered with ~20% travel to fab and packaging facilities as needed; on-site candidates in the preferred location will travel less frequently.
Reports to: Director of Mechanical Engineering
Role type: Full-time, hands-on, high-ownership technical contributor
Mission
Engineer the chip-on-carrier and package-level hardware behind 1AU Technologies’ high-power and high-brightness semiconductor laser diodes — owning the mechanical design solutions that close package-level thermal and reliability budgets driving device performance across defense and commercial applications.
Why this role matters
In high-power and high-brightness semiconductor diodes, package performance is the gating factor on device performance. Thermal resistance from junction to coolant, mechanical stress fields in brittle semiconductor materials, and packaging reliability define what the diode can achieve in the field.
Defense and commercial deployments demand high heat-flux extraction from compact form factors using non-traditional composite materials, all while managing brittle semiconductor materials operating outside the linear-elastic regime.
Closing those margins requires more than CAD execution—it requires a design owner who contributes to package-level performance budgets and drives the analytical trade-offs that translate device requirements into manufacturable packages.
What success looks like (12–18 months)
- Validated chip-on-carrier and package designs delivering specified thermal performance and stress margins under defined operating conditions.
- Closed thermal-resistance and stress budgets ensuring junction-temperature and reliability targets are met.
- Bonding, hermetic-seal, and assembly processes validated for repeatability, yield, and long-term reliability.
- Qualification test campaigns (thermal cycling, shock, lifetime testing) passed against industry standards (Telcordia, JEDEC, MIL-STD).
- Production-ready package designs optimized for manufacturability, yield, and assembly efficiency.
- Mechanical design solutions delivered against closed package-level performance budgets, with documented analytical trade studies driving design decisions across active device platforms.
Core responsibilities
1) Design chip-on-carrier and package-level hardware
- Engineer submounts, carriers, lids, hermetic seals, optical interfaces, and alignment features for high-power and high-brightness laser diodes.
- Implement packing strategy and and develop packaging processes at the machine level with stable and repeatable processes with wide design margins
- Balance heat extraction, mechanical stress, and packaging reliability under tight SWaP constraints.
- Develop modular package architectures that support integration, scaling, and serviceability.
- Translate 2D device designs into manufacturable, SWaP-optimized 3D chip-on-carrier and package designs.
2) Engineer for thermal performance
- Architect heat-extraction paths from junction to coolant, minimizing thermal resistance across the package stack.
- Select and qualify non-traditional thermal composite materials with CTE matching across heterogeneous interfaces.
- Quantify transient and steady-state thermal performance under operational duty cycles.
- Collaborate with thermal and reliability teams to optimize conduction paths and minimize differential expansion.
3) Drive chip-scale FEA across thermal, structural, and brittle-fracture regimes
- Own the mechanical design solution within a device platform.
- Contribute to package-level KPI budgets, distilling figures of merit into actionable design trades.
- Apply brittle fracture mechanics and design discipline outside the linear-elastic regime to manage stress in semiconductor materials.
- Perform design-stage FEA from concept through ~80% confidence in SolidWorks, ANSYS, COMSOL, or similar; coordinate review and handoff to FEA specialists for high-fidelity validation, non-linear modeling, and final qualification.
4) Drive material trade studies for non-traditional thermal composites
- Develop and implement experimental verification trade studies to reduce theory to practice
- Lead material selection across CTE-matched, high-thermal-conductivity composite stacks..
- Quantify performance, manufacturability, and cost trade-offs across candidate materials.
- Partner with materials science to evaluate emerging composites and qualify them for production use.
- Document material rationales tied to package-level performance budgets.
5) Partner with semiconductor process and packaging engineering
- Coordinate with device, fab, and packaging teams to align mechanical design with process realities for reliable and repeatable pack performance.
- Influence process selection (die attach, wire bonding, hermetic packaging) through hands-on packaging knowledge.
- Support process qualification, yield improvement, and root-cause investigations on packaging defects.
6) Support qualification and reliability
- Define qualification plans and resource environmental, lifetime, and stress-testing campaigns aligned with industry standards (Telcordia, JEDEC, MIL-STD).
- Drive package-level failure analysis on returns and qualification anomalies.
- Refine designs based on test feedback to improve yield, reliability, and lifetime margin.
Qualifications
- BS or MS in Mechanical Engineering, Materials Science, Physics, or related field.
- 5–10+ years of experience in semiconductor packaging or chip-on-carrier mechanical design and hands-on implementation.
- Proficient CAD user with experience ingesting 2D device designs, providing feedback to upstream design partners, and translating them into manufacturable, SWaP-optimized 3D chip-on-carrier and package designs.
- Proficiency with semiconductor device physics and packaging principles, including junction heating, current density, and optical-thermal-mechanical interactions.
- Proficiency with chip-scale FEA spanning thermal, structural, and brittle-fracture regimes in SolidWorks, ANSYS, COMSOL, or similar.
- Demonstrated effectiveness as a design contributor to package-level performance budgets.
- Experience taking hardware from concept through qualification against industry packaging standards (Telcordia GR-468, JEDEC JESD22, MIL-STD-883) and applicable MIL and NASA environmental standards.
- Familiarity with TRL frameworks and defense-program qualification milestones.
- Hands-on proficiency in fast-paced, hardware-driven R&D environments — comfortable performing hands-on packaging work in the diode-packaging lab and executing tooling modifications in the machine shop.
- Strong background in:
- Heat transfer and chip-level thermal management
- Thermal expansion, CTE matching, and stress in heterogeneous material stacks
- GD&T and tolerance analysis (especially for hermetic packages)
- Brittle fracture mechanics and design outside the linear-elastic regime
- Must be a U.S. Person as defined under ITAR/EAR.
Nice-to-have
- Experience with high-power semiconductor laser diodes specifically.
- Experience with non-traditional thermal composite materials (copper-diamond, AlSiC, CuMo, AlN, BeO, CuW, or similar).
- Experience with hermetic packaging methods (parallel seam welding, laser sealing, electron-beam welding, or similar).
- Experience with die-attach and bonding processes (AuSn eutectic, indium soldering, transient liquid phase, wire bond, or similar).
- Experience with optical window and mirror bonding methods and adhesives for beam-combining applications.
- Experience with package-level failure analysis (delamination, wire bond lift, die crack, solder voiding).
- Experience writing macros for repetitive engineering workflows (VBA, .NET, or similar).
- Experience with TCAD or device-level simulation informing packaging trade studies.
- Experience with active and advanced thermal management for high-heat-flux applications (microchannel cooling, jet impingement, immersion, phase-change materials, or similar).
Leadership traits we value
- Single-threaded ownership: accountable for package-level mechanical performance and reliability.
- Multi-physics-minded integrator who understands how thermal, mechanical, electrical, and optical behaviors interact at the chip and package level.
- Detail-oriented engineer grounded in first principles and measurable tolerances.
- Clear communicator who turns mechanical and materials constraints into actionable cross-functional decisions.
- Thrives in high-stakes environments where precision and reliability are non-negotiable.
- Engineering problem solver at the core—owns the design solution and drives system-level outcomes through analysis and trade-offs, not just CAD execution.