Job Description

Senior Functional Verification Engineer

Edison Smart are hiring for a Senior Functional Verification Engineer for a European leader in advanced hardware acceleration. You will be a key contributor to the development and validation of next-generation parallel processing architectures and acceleration platforms. You’ll work in a high-impact engineering environment using state-of-the-art verification tools, methodologies, and design flows.

Key Responsibilities

• Define verification strategies and create detailed verification plans

• Develop UVM-based testbenches and verification environments at the IP level

• Design and execute complex SoC-level system tests

• Analyse and monitor functional coverage to ensure thorough verification

• Develop and maintain reference models to enhance validation accuracy

• Collaborate closely with design, architecture, and software teams

• Contribute to technical leadership within small project teams when required

WHAT WE'RE LOOKING FOR

Skills & Experience

• Strong expertise in Functional Verification methodologies and tools

• Proficiency in SystemVerilog UVM and C programming

• Comfortable working in a Linux-based development environment (shell, git/svn, etc.)

• Strong teamwork and cross-functional collaboration skills

• Fluency in French and ability to work effectively in technical English